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65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application

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32 Author(s)
Fung, S.K.H. ; R&D, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan ; Huang, H.T. ; Cheng, S.M. ; Cheng, K.L.
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This paper presents a state-of-the-art 65nm CMOS transistor technology using 300mm bulk substrate. Device offering is classified as High Speed (HS), General Purpose (G) and Low Power (LP) so as to cover the whole foundry application space with various power and performance requirement. High volume manufacturable 55nm / 45nm and <40nm gate length transistor at EOT 1.95nm / 1.4nm and 1.2nm are achieved using thermal cycle reduction together with optimized gate height and gate activation dose. Advantage of Laser Spike Anneal (LSA) over conventional RTA is demonstrated for the first time. NFET poly depletion is reduced by 1 A and drive current is increased by 7%.

Published in:

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

15-17 June 2004