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We have developed a power-aware CMOS technology featuring variable VDD and back-bias control. Three typical operation modes are defined: high-speed mode (VDD = 1.2V, VB = 0V), nominal mode (VDD = 0.9V, VB = -0.5V) and power-save mode (VDD = 0.6V, VB = -2.0V). Compared with nominal mode, one and a half order of magnitude reduction of standby leakage current is achieved with power-save mode, while 75% higher drivability is achieved with high-speed mode. Device reliability for back-bias condition was also investigated. With higher back-bias, NBT (Negative Bias Temperature) degradation for pFET is enhanced especially in the case of thinner gate oxide. From activation energy, we believe the dominant mechanism is SHH (Substrate Hot-Hole) injection. Reduced VDD at standby mode drastically alleviates this degradation caused by NBT stress and SHH injection. With appropriate VDD and VB combination, power-aware 65nm CMOS with sufficient reliability can be achieved.