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PAE/SiOC/SiC hybrid dual damascene process with low-k (k=2.5) dielectric layer for 65nm-node was successfully integrated. The EB curing technique of the low-k dielectric was selected to maintain enough adhesion strength. Package feasibility test was performed successfully. To evaluate the impact of the ILD process on the device performance, gate oxide characteristics was carefully studied and no degradation was observed. Functional logic and memory blocks were fabricated using multi level interconnections. High manufacturability of the hybrid DD interconnects process for the 65nm CMOS platform is demonstrated.
Date of Conference: 15-17 June 2004