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Systematic study of pFET Vt with Hf-based gate stacks with poly-Si and FUSI gates

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22 Author(s)
Cartier, E. ; IBM Semicond. Res. & Dev. Center, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Narayanan, V. ; Gusev, E.P. ; Jamison, P.
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The flatband/threshold voltages (Vfb/Vt) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO2 at poly-Si deposition temperatures is identified as the root cause for the poor Vfb/Vt control. No improvement in Vt control is obtained by engineering physically closed Si3N4 barrier layers on HfO2. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large Vfb/Vt shifts are observed with HfO2. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al2O3 cap layers on silicates.

Published in:

VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

15-17 June 2004