By Topic

Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
P. K. Samudrala ; Space Micro Inc., San Diego, CA, USA ; J. Ramos ; S. Katkoori

We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit. The circuit can be hardened against SEUs by selectively applying triple modular redundancy (STMR) to these sensitive subcircuits. However, there is an increase in the number of the voter circuits required for the STMR circuits. Virtex has abundant number of tri-state buffers that can be employed to construct SEU immune majority voter circuits. We also present a SEU fault insertion simulator designed to introduce errors representing SEUs in the circuits. STMR method is thoroughly tested on MCNC'91 benchmarks. With a small loss of SEU immunity, the proposed STMR method can greatly reduce the area overhead of the hardened circuit when compared to the state-of-the-art triple modular redundancy (TMR). STMR method along with the readback and reconfiguration feature of Virtex can result in very high SEU immunity.

Published in:

IEEE Transactions on Nuclear Science  (Volume:51 ,  Issue: 5 )