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We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit. The circuit can be hardened against SEUs by selectively applying triple modular redundancy (STMR) to these sensitive subcircuits. However, there is an increase in the number of the voter circuits required for the STMR circuits. Virtex has abundant number of tri-state buffers that can be employed to construct SEU immune majority voter circuits. We also present a SEU fault insertion simulator designed to introduce errors representing SEUs in the circuits. STMR method is thoroughly tested on MCNC'91 benchmarks. With a small loss of SEU immunity, the proposed STMR method can greatly reduce the area overhead of the hardened circuit when compared to the state-of-the-art triple modular redundancy (TMR). STMR method along with the readback and reconfiguration feature of Virtex can result in very high SEU immunity.