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System-level design hardening based on worst-case ASET Simulations

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6 Author(s)
Y. Boulghassoul ; Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA ; P. C. Adell ; J. D. Rowe ; L. W. Massengill
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We present experimental and simulation results on single-event transients in an analog subsystem for satellite electronic equipment. Investigations based on worst-case transient events, simulated with transistor-level circuit models, suggest design modifications for hardening.

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IEEE Transactions on Nuclear Science  (Volume:51 ,  Issue: 5 )