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The use of a new frequency compensation scheme for a three-stage operational amplifier is presented. The use of a positive feedback compensation (PFC) is employed to improve frequency response when compared to nested Miller compensation. A set of design equations is derived to give insight into the sizing of the amplifier. In addition, some characteristics relevant to the low-voltage low-power circuits using operational amplifiers have been modeled. Finally, an optimization algorithm was used with the purpose of extracting the most efficient solution. The PFC is especially suitable for driving large capacitance loads. It improves frequency response, slew rate (SR), and settling time. Small compensation capacitors make it appropriate for integration in commercial CMOS processes. With an active area of 0.03 mm2 and working at 1.5 V, the circuit dissipates 275 μW, has more than a 100-dB gain, a gain bandwidth of 2.7 MHz, and 1.0 Vμs average SR while driving a 130-pF load. Both measured frequency and transient step response show that the amplifier is stable.