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Architectural support for enhanced SMT job scheduling

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4 Author(s)
Settle, A. ; Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA ; Kihm, J. ; Janiszewski, A. ; Connors, D.

By converting thread-level parallelism to instruction level parallelism, simultaneous multithreaded (SMT) processors are emerging as effective ways to utilize the resources of modern superscalar architectures. However, the full potential of SMT has not yet been reached as most modern operating systems use existing single-thread or multiprocessor algorithms to schedule threads, neglecting contention for resources between threads. To date, even the best SMT scheduling algorithms simply try to group threads for co-residency based on each thread's expected resource utilization but do not take into account variance in thread behavior. As such, we introduce architectural support that enables new thread scheduling algorithms to group threads for co-residency based on fine-grain memory system activity information. The proposed memory monitoring framework centers on the concept of a cache activity vector, which exposes runtime cache resource information to the operating system to improve job scheduling. Using this scheduling technique, we experimentally evaluate the overall performance improvement of workloads on an SMT machine compared against the most recent Linux job scheduler. This work is first motivated with experiments in a simulated environment, then validated on a hyperthreading-enabled Intel Pentium-4 Xeon microprocessor running a modified version of the latest Linux kernel.

Published in:

Parallel Architecture and Compilation Techniques, 2004. PACT 2004. Proceedings. 13th International Conference on

Date of Conference:

29 Sept.-3 Oct. 2004

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