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Evaluating schedulers for multimedia processing on buffer-constrained SoC platforms

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4 Author(s)
Maxiaguine, A. ; Swiss Fed. Inst. of Technol., Zurich, Switzerland ; Kunzli, S. ; Thiele, L. ; Chakraborty, S.

Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real-time scheduling and accurately captures the variability in task execution requirements.

Published in:

Design & Test of Computers, IEEE  (Volume:21 ,  Issue: 5 )