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This paper proposes a field programmable VLSI processor (FPVLSI) based on a bit-serial mesh-connected cellular array that reduces complexity of a programmable interconnection network. A cell is capable of performing operations, storing intermediate results, and controlling bit-serial operations. To implement these three functions efficiently, the cell consists of shift-register-based lookup tables. Moreover, direct allocation of a control/data flow graph (CDFG) is employed where only a single node in a CDFG is mapped into a single cell so that the interconnection complexity is greatly reduced. The FPVLSI with 64 cells is designed in a 0.18μm CMOS design rule. The estimated performance of the FPVLSI is evaluated to be 9 times higher than that of the conventional FPGA in a typical application.