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A high-level implementation of a high performance pipeline FFT on Virtex-E FPGAs

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2 Author(s)
Sukhsawas, S. ; Sch. of Comput. Sci., Queen''s Univ. Belfast, UK ; Benkrid, K.

This paper presents a high-level implementation of pipeline FFT. The design has been coded in Handel-C language and targeted Xilinx Virtex-E FPGA series. It is fully implemented and tested on real hardware using Celoxica RC1000-PP prototyping board. The implementation results show that our implementation outperforms other implementation of FFT on the same series of FPGA. An implementation of 1024-point FFT on Virtex-E can run at a maximum clock frequency of 82 MHz leading to a 82 MS/s throughput compared with the Xilinx core of the same size that can run at a maximum clock frequency of 83 MHz but with only 21 MS/s throughput. The design is parameterizable in terms of input wordlength, Twiddle factors wordlength and processing wordlength. It is scalable in terms of number of stages which means that a 16-point, 64-point, 256-point and 1024-point or higher power-of-4 complex-point FFT can be synthesized from the same code. The paper reports the fastest 1024-point FFT implementation on Virtex-E FPGA platform.

Published in:

VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on

Date of Conference:

19-20 Feb. 2004