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Behavioural scheduling to balance the bit-level computational effort

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4 Author(s)
Molina, M.C. ; Dpto. Arquitectura de Computadores y Automatica, Univ. Complutense de Madrid, Spain ; Ruiz-Sautua, R. ; Mendias, J.M. ; Hermida, R.

Conventional synthesis algorithms schedule multiple precision specifications (formed by operations of different widths) by balancing the number of operations of every different type and width executed per cycle. However, totally balanced schedules are not always possible, even for specifications with a unique width, and therefore some hardware waste appears. In this paper a heuristic scheduling algorithm to minimize this hardware waste is presented. It successively transforms specification operations into sets of smaller ones which are scheduled independently, until the most uniform distribution of the computational effort of operations among cycles is achieved. In consequence some specification operations may be executed during a set of non-consecutive cycles, and over several linked hardware resources. In combination with allocation algorithms able to guarantee the bit-level reuse of hardware resources, our approach substantially reduces datapath area. Additionally, in most cases clock cycles length is also lessened.

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VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on

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