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System-level design techniques for throughput and power optimization of multiprocessor SoC architectures

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4 Author(s)
Srinivasan, K. ; Dept. of Comput. Sci. & Eng., Arizona State Univ., Tempe, AZ, USA ; Telkar, N. ; Ramamurthi, V. ; Chatha, K.S.

Innovative system-level computer-aided design techniques are required for optimizing the performance and power of applications that are mapped to multiprocessor system-on-chip (SoC) architectures. The paper addresses the hitherto unexplored problem of system-level low power design of multimedia and network processing applications with deadline greater than period. This paper presents four techniques that combine low power optimizations (namely dynamic voltage and frequency scaling (DVS) and dynamic power management (DPM)) with loop transformations (functional pipelining and unrolling) to minimize the power consumption, while satisfying the period and deadline constraints of the application. The strengths of the techniques lie in their low complexity and large power consumption savings when compared with existing heuristic based approaches, and close to optimum results when compared with our ILP based approach (presented elsewhere stated in K. Srinivasan and K.S. Chatha (2004)). All our techniques result in large system-level power reductions when compared with existing heuristic approaches (max: 55.45%, min: 28.60%, ave: 42.02%). Further, the results produced by our deterministic and stochastic techniques for realistic benchmarks are on an average within 12.07% and 4.125%, respectively of the optimum solution produced by the ILP based approach. Our heuristic techniques are faster than the ILP based approach by several orders of magnitude.

Published in:

VLSI, 2004. Proceedings. IEEE Computer society Annual Symposium on

Date of Conference:

19-20 Feb. 2004