Cart (Loading....) | Create Account
Close category search window
 

Stacked modular package

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Pienimaa, S.K. ; Nokia Corp., Helsinki, Finland ; Miettinen, J. ; Ristolainen, E.

This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is a cost-effective solution to save placement and routing area on the board. Furthermore, a vertical module enables the benefit of several IC processes in the same module. The goal was to develop a method to produce a stacked modular package on a small scale, and to verify the feasibility of the solution. The main focus has been to test the bare die connections to the interposer and the vertical connections between interposers. The structure enables also, e.g., thin discretes, and passive arrays to be assembled on the interposer, thus enabling system-in-package (SiP) solutions. The method has been tested using thin daisy chain dice and daisy chain vertical interconnections. The dimensions of the developed six chip modules were 14×8×0.8-1 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were either 100 or 150-μm thick, and the chips were thinned down to 90 μs. Eutectic tin-lead solder bumps were used to mount the flip chips to the interposer. Solder-coated polymer spheres were used to stack the interposers on top of each other. The developed stacking process and vertical area interconnections by plastic core balls give good reliability and uniform stand-off height. Thermal cycling test +125/-40°C until 2000 cycles proved reliability of the structure. Flip-chip failures were found after 500 cycles and only 1 of 32 vertical connection failures occurred during the test. Furthermore, this was caused, at least partly, by excess solder. Plastic ball as interconnection media between stacked layers gives good reliability and uniform stand-off height.

Published in:

Advanced Packaging, IEEE Transactions on  (Volume:27 ,  Issue: 3 )

Date of Publication:

Aug. 2004

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.