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Fabrication process for Josephson computer ETL-JC1 using Nb tunnel junctions

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4 Author(s)
Nakagawa, H. ; Electrotech. Lab., Ibaraki, Japan ; Kurosawa, I. ; Aoyagi, M. ; Takada, S.

The fabrication process that was used to develop a multichip Josephson computer named ETL-JC1 is described. The ETL-JC1 consists of four Josephson LSI chips: a register arithmetic logic unit chip (RALU), a sequence control unit chip (SQCU), a 1280-b read-only memory chip (IROU), and a 1-kb random access memory chip (DRAU). The fabrication process, based on a 3-μm Nb/AlOx/Nb junction technology, has been developed to make a complete set of the Josephson LSI chips. The present fabrication process includes a trilayer tunnel junction formation, a Nb underlayer method, a self-aligned insulation method, a reactive ion etching (RIE) process, an etching stopper layer formation, and a superconducting contact formation. The Josephson critical current density was controlled by the oxidation time within the fluctuation of ±20% in the LSI fabrication runs. The resistors were made of palladium metal film on the LSI chips. The sheet resistance was controlled within the fluctuation between -12.5% and +19% in the LSI runs. It was found that the Josephson LSI chips fabricated by this process showed a high reliability for a long-term storage at room temperature and thermal cyclings between 4.2 K and room temperature without any passivation layers on the LSI surface

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Magnetics, IEEE Transactions on  (Volume:27 ,  Issue: 2 )