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Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification

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7 Author(s)
R. Y. Zhan ; Illinois Institute of Technology ; H. G. Feng ; Q. Wu ; X. K. Guan
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On-chip ESD (electrostatic discharging) protection is a challenging IC design problem New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification, which has been used to develop the first intelligent CAD tool of such kind. Design examples in 0.35μm BiCMOS are presented.

Published in:

Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific

Date of Conference:

27-30 Jan. 2004