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Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)

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2 Author(s)
Aviral Shrivasta ; Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA ; Dutt, N.

Energy consumption is emerging as a critical design concern for programmable embedded systems. Many reduced bit-width instruction set architectures (rISA) (e.g., ARM Thumb) are being increasingly used to decrease code size. Previous work has explored energy savings in noncached rISA architectures as a byproduct of code size reduction. We present an energy efficient code generation technique for rISA architectures, and furthermore explore energy savings for both cached and noncached architectures. Our code generation technique uses profile information to find the most frequently executed parts of the program. By aggressively reducing code size on frequently executed parts, fewer fetches to instruction memory are incurred, thus reducing the power consumption of the instruction memory. We achieve an average 30% reduction in instruction memory energy consumption in cached systems, on a variety of benchmarks, as compared to non-rISA architectures.

Published in:

Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific

Date of Conference:

27-30 Jan. 2004