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A thread partitioning algorithm in low power high-level synthesis

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4 Author(s)
Uchida, J. ; Dept. of Comput. Sci., Waseda Univ., Tokyo, Japan ; Togawa, Nozomu ; Yanagisawa, M. ; Ohtsuki, T.

We propose a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe parallel behaving circuit blocks (threads) explicitly. First it focuses on a local register file RF in a thread. It partitions a thread into two subthreads, one of which has RF and the other does not have RF. The partitioned subthreads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned subthreads have waiting time for synchronization, gated clocks can be applied to each subthread. Then we can synthesize a low power circuit with a low area overhead, compared to the original circuit. Experimental results demonstrate effectiveness and efficiency of the algorithm.

Published in:

Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific

Date of Conference:

27-30 Jan. 2004

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