A self-aligned process for high-voltage, short-channel vertical DMOSFETs in 4H-SiC

In this paper, we describe a self-aligned process to produce short-channel vertical power DMOSFETs in 4H-SiC. By reducing the channel length to /spl les/0.5 /spl mu/m, the specific on-resistance of the MOSFET channel is proportionally reduced, significantly enhancing performance.