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InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

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12 Author(s)
Sokolich, M. ; HRL Labs. LLC, Malibu, CA, USA ; Chen, M.Y. ; Rajavel, R.D. ; Chow, D.H.
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We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with ft>250 GHz and DHBT with ft>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.

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Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 10 )