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An intrinsic delay extraction method for Schottky gate field effect transistors

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1 Author(s)
Suemitsu, T. ; NTT Photonics Labs., Kanagawa, Japan

This letter reports a new method for extracting the intrinsic transit delay associated with the carrier transport under the gate of field-effect transistors (FETs). With this method, the parasitic charging time is ruled out by the de-embedding used to strip the pad parasitics. Therefore, the intrinsic transit delay and the drain delay associated with the extended depletion region toward drain electrode can be separated without the influence of the parasitic charging time, as proven by an analysis of short-channel InP-based high electron mobility transistors. The method is applicable to any type of Schottky-gate FETs and could be helpful for studying the effective carrier velocity in the gate region of FETs.

Published in:

Electron Device Letters, IEEE  (Volume:25 ,  Issue: 10 )

Date of Publication:

Oct. 2004

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