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Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains

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1 Author(s)
Pomeranz, I. ; Sch. of Electr. & Comput. Eng., Purdue Univ., Lafayette, IN, USA

For a scan design with multiple scan chains, we say that a scan chain is P-testable if it is possible to achieve complete fault coverage for the circuit (i.e., detect all the detectable target faults) when the scan chain is driven from a source that produces values having a property P. For example, a scan chain is random-testable if it is possible to achieve complete fault coverage for the circuit when the scan chain is driven from a source of pseudorandom values for the complete test application process. In a similar way, we define periodic-testable and combination-testable scan chains. All the sources we consider for P-testable scan chains are simple to implement on-chip. By identifying P-testable scan chains and driving them from the appropriate on-chip sources, we reduce the number of scan chains that need to be driven from an external tester. In this way, we reduce the number of scan inputs that a tester needs to control and the amount of test data that the external tester needs to store and apply to the circuit. Existing test data compression techniques can be used to further reduce the test data volume.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:23 ,  Issue: 10 )