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ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

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7 Author(s)
Rouying Zhan ; Dept. of Electr. & Comput. Eng., Illinois Inst. Technol., Chicago, IL, USA ; Haigang Feng ; Qiong Wu ; Haolu Xie
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On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-μm BiCMOS technology.

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:23 ,  Issue: 10 )