Referenced Items are not available for this document.
On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-μm BiCMOS technology.
Published in:
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
(Volume:23
,
Issue:
10
)
Date of Publication: Oct. 2004
- Page(s):
- 1421 - 1428
- ISSN :
- 0278-0070
- INSPEC Accession Number:
- 8144621
- Digital Object Identifier :
- 10.1109/TCAD.2004.833613
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 27 September 2004
- Issue Date :
- Oct. 2004
- Sponsored by :
- IEEE Council on Electronic Design Automation
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