Referenced Items are not available for this document.
Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device simulators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit. For the first time, both the I-V and the C-V characteristics of the device have been efficiently modeled for circuit simulations. The model so developed has been used to simulate arithmetic and logic blocks using HSPICE.
Published in:
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
(Volume:23
,
Issue:
10
)
Date of Publication: Oct. 2004
- Page(s):
- 1411 - 1420
- ISSN :
- 0278-0070
- INSPEC Accession Number:
- 8144620
- Digital Object Identifier :
- 10.1109/TCAD.2004.835135
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 27 September 2004
- Issue Date :
- Oct. 2004
- Sponsored by :
- IEEE Council on Electronic Design Automation
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