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Assessment of on-chip wire-length distribution models

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3 Author(s)
M. Y. Lanzerotti ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; G. Fiorenza ; R. A. Rand

Ultralarge-scale integrated (ULSI) chip design data is needed for an assessment of existing on-chip wirelength distribution models. Data extracted from modern chips such as high-performance microprocessors provide information about actual wire length requirements in ULSI chip designs. These requirements are compared with wirelength estimates obtained by evaluating existing models as functions of Rent's parameters that are extracted from the designs. This brief assesses the extent to which existing models estimate wirelength requirements in 100 ASIC-like control logic designs in the 1.3-GHz POWER4 microprocessor. For each design, physical design characteristics and wirelength requirements are measured and compared with model estimates. Lack of agreement between the data and models is observed for most designs, and possible reasons for the lack of agreement are discussed.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:12 ,  Issue: 10 )