By Topic

Low-power and high-performance equality comparator using pseudo-NMOS NAND gates

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kim, C.-Y. ; Dept. of EECS, KAIST, Daejeon, South Korea ; Kim, L.-S.

An equality comparator (EC), which exploits the fact that unequal cases happen more frequently in compare operations, is proposed. It is composed of conditional pseudo-NMOS NAND gates to save the power of the unused sub-ECs. The proposed 64-bit EC results in 31% faster speed and 42% less power dissipation than the conventional dynamic EC.

Published in:

Electronics Letters  (Volume:40 ,  Issue: 18 )