By Topic

Area efficient, low power and robust design for add-compare-select units

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Akbari, M.K. ; Dept. of Comput. Eng. & Inf. Technol., Amirkabir Univ. of Technol., Tehran, Iran ; Jahanian, A. ; Naderi, M. ; Javadi, B.

This paper presents an area efficient, low-power and robust ACS unit for Viterbi decoder in two synchronous and asynchronous architectures. The asynchronous design is based upon quasi delay insensitive (QDI) timing model which leads to a robust and low power purpose and synchronous architecture uses a hybrid CMOS-pseudo NMOS technology to improve area and throughput factors. Some optimization techniques to reduce the power and area are applied to each design. The simulation results show the asynchronous design has the lowest power consumption with 6.65mW and hybrid CMOS has the lowest transistor counts with 759 in relative to other reported circuits.

Published in:

Digital System Design, 2004. DSD 2004. Euromicro Symposium on

Date of Conference:

31 Aug.-3 Sept. 2004