By Topic

Power consumption characterization and modeling of embedded memories in XILINX

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Elleouet, D. ; LESTER Lab., South-Brittany Univ., Lorient, France ; Julien, N. ; Houzet, D. ; Cousin, J.-G.
more authors

To increase their flexibility, latest FPGA devices integrate processors, arithmetics elements and memories; but these programmable circuits have a significant power consuming, which grows up at each process generation. Then it is necessary to develop reliable high-level power consumption models in order to estimate and reduce the power budget as soon as possible in the design flow. Among the FPGA modeling methods, none has integrated the embedded memory yet. We propose here a power model of embedded memory for the Xilinx Virtex 400E based on physical measurements combined with algorithmic and architectural parameters. This simple model is validated in comparison to Xilinx's estimation tool XPOWER and an example of memory architecture design illustrates the interest of such an approach.

Published in:

Digital System Design, 2004. DSD 2004. Euromicro Symposium on

Date of Conference:

31 Aug.-3 Sept. 2004