By Topic

VLSI design of a digital RFI cancellation scheme for VDSL transceivers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Fanucci, L. ; National Res. Council, Pisa, Italy ; Locatelli, R. ; Petri, E.

In this paper, a digital RFI (radio frequency interference) canceller for DMT (discrete multitone modulation)-based VDSL (very high-speed digital subscriber line) systems is presented. The adopted algorithm is optimized in terms of performance vs. complexity and size of the involved memories. High level, maximum precision system simulations showed the effectiveness of the cancellation scheme, considering VDSL performance parameters such as bit rate and efficiency in counteracting performance degradation due to RFI. The canceller has been implemented as a hardware macro-cell: the design space already explored at algorithm level to meet a good complexity/performance trade-off, has been deeply investigated during the bit true analysis to fix the finite numeric representation, the micro-architecture definition and the final technology mapping. Results of logic synthesis on a standard cells 0.18 μm CMOS technology are reported, in terms of area and energy consumption.

Published in:

Digital System Design, 2004. DSD 2004. Euromicro Symposium on

Date of Conference:

31 Aug.-3 Sept. 2004