VLSI design of a digital RFI cancellation scheme for VDSL transceivers

In this paper, a digital RFI (radio frequency interference) canceller for DMT (discrete multitone modulation)-based VDSL (very high-speed digital subscriber line) systems is presented. The adopted algorithm is optimized in terms of performance vs. complexity and size of the involved memories. High level, maximum precision system simulations showed the effectiveness of the cancellation scheme, considering VDSL performance parameters such as bit rate and efficiency in counteracting performance degradation due to RFI. The canceller has been implemented as a hardware macro-cell: the design space already explored at algorithm level to meet a good complexity/performance trade-off, has been deeply investigated during the bit true analysis to fix the finite numeric representation, the micro-architecture definition and the final technology mapping. Results of logic synthesis on a standard cells 0.18 /spl mu/m CMOS technology are reported, in terms of area and energy consumption.