By Topic

ASSEC: an asynchronous self-checking RISC-based processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hyde, P.D. ; Sch. of Electr., Electron. & Comput. Eng., Newcastle Univ., Newcastle upon Tyne, UK ; Russell, G.

The use of deep submicron technology raises a number of concerns about reliability in VLSI circuits. Shrinking geometries and reduced power supplies leave the circuits vulnerable to 'soft' and transient errors. The combination of high clock speed and large circuit area result in high power consumption and skew in clock distribution. This paper investigates the use of concurrent error detection (CED) and asynchronous design to overcome these problems. Four pipelined processor designs are compared - two synchronous, two asynchronous with one of each type using CED. Initial results indicate an area overhead of 12% in return for a fault coverage of 98.54% of all unidirectional errors. Additionally, the asynchronous CED processor has an area overhead of only 4% when compared to the synchronous nonCED design.

Published in:

Digital System Design, 2004. DSD 2004. Euromicro Symposium on

Date of Conference:

31 Aug.-3 Sept. 2004