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A 90nm dual-port SRAM with 2.04 μm2 8T-thin cell using dynamically-controlled column bias scheme

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5 Author(s)
K. Nii ; Renesas Technology, Itami, Japan ; Y. Tsukamoto ; T. Yoshizawa ; S. Imaolka
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A high-density dual-port SRAM (DP-SRAM) with a 2.04 μm2 cell size is implemented in 90 nm CMOS technology. A dynamically-controlled column-bias scheme is presented, which reduces the active power by 64% and the stand-by current by 93%.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004