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A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter

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2 Author(s)
Nair, K. ; Minnesota Univ., Minneapolis, MN, USA ; Hariani, R.

A 96 dB SFDR 50 MS/s pipeline A/D converter has been designed in a 0.25 μm CMOS process. An improved sample-and-hold and subtractive dither-continuous gain correction (SD-CGC) digital calibration are used to increase linearity. Prototype measurements show that the SNDR increases from 49 dB to 75 dB and the SFDR increases from 62 dB to 96 dB using the technique.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004