A 15 b 20 MS/s CMOS pipelined ADC with digital background calibration

A 15 b 20 MS/s CMOS pipelined ADC is fabricated in a 0.18 /spl mu/m dual-gate CMOS technology and achieves 94 dB SFDR and 74 dB SNDR for a 8 MHz input. Digital calibration can proceed continuously in the background to maintain the ADC resolution. The chip occupies an area of 3.3/spl times/3.4 mm/sup 2/ and dissipates 235 mW with 1.8 V and 3.3 V dual supplies.