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A 15 b 20 MS/s CMOS pipelined ADC with digital background calibration

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3 Author(s)
Hung-Chih Liu ; Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan ; Zwei-Mei Lee ; Jieh-Tsorng Wu

A 15 b 20 MS/s CMOS pipelined ADC is fabricated in a 0.18 μm dual-gate CMOS technology and achieves 94 dB SFDR and 74 dB SNDR for a 8 MHz input. Digital calibration can proceed continuously in the background to maintain the ADC resolution. The chip occupies an area of 3.3×3.4 mm2 and dissipates 235 mW with 1.8 V and 3.3 V dual supplies.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004