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A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC

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2 Author(s)
E. Siragusa ; Univ. of California San Diego, La Jolla, CA, USA ; I. Galton

A 1.8 V 15 b 40 MS/s CMOS pipelined ADC with 90 dB SFDR and 72 dB peak SNR over the full Nyquist band is described. ADC performance is enhanced by digital background calibration of DAC noise and interstage gain error. The IC is realized in a 0.18 μm CMOS process, consumes 400 mW, and has a die size of 4 mm×5 mm.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004