By Topic

A dual-core 64 b UltraSPARC microprocessor for dense server applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

12 Author(s)
Takayanagi, T. ; Sun Microsystems, Sunnyvale, CA, USA ; Shin, J.L. ; Petrick, B. ; Su, J.
more authors

A processor core, previously implemented in a 0.25 μm Al process, is redesigned for a 0.13 μm Cu process to create a dual-core processor with 1 MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applications. Circuit design challenges, including negative bias temperature instability (NBTI), leakage and coupling noise are discussed.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004