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A 3.3 V 4 Gb four-level NAND flash memory with 90 nm CMOS technology

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13 Author(s)
Seungjae Lee ; Samsung Electron., Hwasung, South Korea ; Young-Taek Lee ; Wook-Kee Han ; Dong-Hwan Kim
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A 4 Gb NAND flash memory with 2 b/cell uses 90 nm CMOS to achieve simultaneous data load during program operation with 1.6 MB/s program throughput. Fuse or pad-bonding switches it to a 2 Gb 1 b/cell NAND flash memory. The row decoder located in the middle of the cell array reduces W/L rise time and coupling noise. A program-after-erase technique and lowered floating poly thickness minimize cell Vth distribution.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004