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A 0.18 μm 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

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15 Author(s)
Woo Yeong Cho ; Samsung Electron., Hwasung, South Korea ; Beak-Hyung Cho ; Byung-Gil Choi ; Hyung-Rok Oh
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A non-volatile 64 Mb phase-transition RAM is developed by fully integrating a chalcogenide alloy GST (Ge2Sb2Te5) into 0.18 μm CMOS technology. This alloy is programmed by resistive heating. To optimize SET/RESET distribution, a 512 kb sub-core architecture, featuring meshed ground line, is proposed. Random read access and write access for SET/RESET are 60 ns, 120 ns and 50 ns, respectively, at 3.0 and 30°C.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004