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Design and optimization of buffer chains and logic circuits in a BiCMOS environment

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2 Author(s)
Elrabaa, M.S. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Elmasry, M.I.

The design and optimization of BiCMOS buffer chains and multi level logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multi level CML (current mode logic) gates is also studied

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Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 5 )