Referenced Items are not available for this document.
We explore tradeoffs between organization and number of ALUs and clock frequency in a stream processor. The tool provides candidate low-power configurations and estimates of their real-time performance. The tool relates instruction-level, subword, and data parallelism to functional units' organization and utilization. The exploration methodology is applicable to all embedded-processor designs in signal and media processing.
Published in:
Micro, IEEE
(Volume:24
,
Issue:
4
)
Date of Publication: July-Aug. 2004
- Page(s):
- 54 - 66
- ISSN :
- 0272-1732
- INSPEC Accession Number:
- 8098534
- Digital Object Identifier :
- 10.1109/MM.2004.25
- Date of Current Version :
- 03 September 2004
- Issue Date :
- July-Aug. 2004
- Sponsored by :
- IEEE Computer Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
