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Integrating cache coherence protocols for heterogeneous multiprocessor systems. 1

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3 Author(s)
Taeweon Suh ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Lee, H.-H.S. ; Blough, D.M.

This systematic methodology maintains cache coherency in a heterogeneous shared-memory multiprocessor system on a chip. It works with any combination of processors that support any invalidation-based protocol, and experiments have demonstrated up to a 51 percent performance improvement, compared to a pure software solution.

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Micro, IEEE  (Volume:24 ,  Issue: 4 )