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14.9 ps/2.2 mW charge-buffered active-pull-down ECL circuit

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3 Author(s)
Chin, K. ; IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Chuang, C.-T. ; Warnock, J.D.

An ECL circuit with a charge-buffered active-pull-down emitter-follower stage is described. Implemented in a 0.8 mu m double-poly trench-isolated selfaligned bipolar process, unloaded gate delays of 14.9 ps/2.2 mW, 20.7 ps/1.2 mW, and 24.5 ps/0.77 mW have been achieved.

Published in:

Electronics Letters  (Volume:28 ,  Issue: 7 )