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RTL/ISS co-modeling methodology for embedded processor using SystemC

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4 Author(s)
Yuyama, Y. ; Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan ; Aramoto, M. ; Kobayashi, K. ; Onodera, Hidetoshi

We propose ISS/RTL co-modeling methodology by describing both in common source file using SystemC. Our method enables rapid and easy generation/verification of RTL/ISS of customizable processor. We apply this method to processor "MiU-Processor". As a result coded-sharing ratio is 67%. For adding new instruction, we add only 12 lines to RTL/ISS shared apart. Our ISS generation method is very effective for multi customizable SoC.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:5 )

Date of Conference:

23-26 May 2004