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ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

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4 Author(s)
Rouying Zhan ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; Haigang Feng ; Haolu Xie ; Albert Wang

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a smart parametric checking mechanism and the first intelligent CAD tool, entitled ESDInspector, developed for full-chip ESD protection circuitry design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35μm BiCMOS.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:5 )

Date of Conference:

23-26 May 2004