By Topic

ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Rouying Zhan ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; Haigang Feng ; Haolu Xie ; A. Wang

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a smart parametric checking mechanism and the first intelligent CAD tool, entitled ESDInspector, developed for full-chip ESD protection circuitry design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35μm BiCMOS.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:5 )

Date of Conference:

23-26 May 2004