By Topic

A systematic approach for analyzing fast addition algorithms using counter tree diagrams

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Homma, N. ; Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; Sakiyama, J. ; Wakamatsu, T. ; Aoki, T.
more authors

This work presents a unified representation of fast addition algorithms based on counter tree diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include redundant-binary (RB) adders, signed-digit (SD) adders, positive-digit (PD) adders, carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. In this paper, we focus on an application of CTDs to the analysis of two-operand RB adders with limited carry propagation. The analysis result shows that there exists possible two types 3-stage CTDs for the RB adders. From this result, we can confirm that well-known RB adders are classified into one of the two types.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:5 )

Date of Conference:

23-26 May 2004