By Topic

Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kakani, V. ; Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA ; Dai, F.F. ; Jaeger, R.C.

This paper presents a delay analysis for Current Mode Logic (CML) circuits operating at the GHz range. The optimal biasing for CML circuits is obtained considering the circuit speed and power consumption. We propose and analyze a novel "keep alive" CML circuit that biases the upper level transistors at the slightly higher current than the lower level transistors. A speed improvement of about 11% at low bias range is demonstrated using the proposed biasing scheme.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:2 )

Date of Conference:

23-26 May 2004