Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits

This paper presents a delay analysis for Current Mode Logic (CML) circuits operating at the GHz range. The optimal biasing for CML circuits is obtained considering the circuit speed and power consumption. We propose and analyze a novel "keep alive" CML circuit that biases the upper level transistors at the slightly higher current than the lower level transistors. A speed improvement of about 11% at low bias range is demonstrated using the proposed biasing scheme.