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This paper proposes, investigates, and reports the results of implementation of asynchronous pipelined circuits in MOS current mode logic (MCML). Asynchronous MCML pipelined circuits combine the potential advantages of MCML and asynchronous circuits to improve performance, to reduce energy consumption, and to provide an analog-friendly environment. The paper introduces a MCML C-element gate and a MCML double-edge-triggered flip-flop to be used in the so-called micropipeline circuits. Based on the post-layout extracted simulation results, an asynchronous MCML FIFO implemented in a standard 0.18 μm CMOS technology demonstrates a throughput of 5 GHz and dissipates 1.25 mW. The MCML micropipeline control circuit dissipates up to four times less energy compared to a conventional static CMOS control circuit with the same throughput.