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Low-power parallel tree architecture for full search block-matching motion estimation

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3 Author(s)
Siou-Shen Lin ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Po-Chih Tseng, ; Liang-Gee Chen

In this paper, a novel low-power parallel tree architecture is proposed for full search block-matching motion estimation. The parallel tree architecture exploits the spatial data correlations between parallel candidate block searches for data sharing, which effectively eliminates huge amount of data access bandwidth while consumes fewer hardware resources compared with array-based architectures. Combining with adaptive parallel partial distortion elimination algorithm, the required average clock cycle count for each macroblock search can be greatly reduced to below 50% to achieve low-power operation. Besides, this architecture can also eliminate redundant computation without pipeline latency and excess power consumption caused by register shifting and redundant memory accessing in array-based architectures. The proposed architecture is suitable for high-end real-time portable video encoding system, which desires high-quality video but low-power consumption.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:2 )

Date of Conference:

23-26 May 2004