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This paper presents a novel embedded memory architecture for real-time mesh-based motion estimation. The proposed architecture stores the reference and the current frames and computes in memory the mesh nodes motion vectors. It uses regular triangular mesh structure. Parallel and pipelined implementations have been used to overcome the huge computational requirements of the motion estimation process. The proposed architecture has been designed, prototyped, and simulated for 0.18 μm CMOS TSMC technology. It can process 37 frames per second at 100 MHz clock frequency. It has a core area of 37.78 mm2, which includes 30.59 mm2 embedded SRAM to store two CIF frames.
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on (Volume:2 )
Date of Conference: 23-26 May 2004