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CMOS APS imager employing 3.3 V 12 bit 6.3 MS/s pipelined ADC

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3 Author(s)
Hamami, S. ; VLSI Syst. Center, Ben-Gurion Univ., Beer-Sheva, Israel ; Fleshel, L. ; Yadid-Pecht, O.

A novel 256×256 CMOS active pixel sensor (APS) system with 12 bit, 6.3 Msample/s (MS/s) CMOS pipelined analog to digital converter (ADC) integrated on chip is presented. The test chip has been implemented in 0.35 μm 2P4M process, operated by a 3.3 V supply and is expected to dissipate 55 mW. The total area of the prototype is 12 mm2, and the core area of ADC is 18% from the total area. System architecture and operation are discussed and simulation results are presented.

Published in:

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on  (Volume:4 )

Date of Conference:

23-26 May 2004